Camtek is proud to announce that it has earned the exclusive Intel EPIC Supplier Award for 2025. This award recognizes the ...

More and better screening of diced dies is essential to meet the quality and cost goals of the 2.5D/3D-IC era.

OpenLight, the world leader in custom PASIC chip design and manufacturing, today announced a new ecosystem partnership with ...

Russia's ZNTC and Belarus's Planar have completed the development of a 350nm-class lithography system, but despite its symbolic value, the machine lags far behind global standards.

As the ultrathin wafers undergo lithography patterning, PECVD, reflow, dicing, and debonding (carrier removal), damage is the greatest threat to yield. Still other problems can arise, as well, due to ...

But the test wafers suggest that Intel is on pace, or maybe even a bit ahead of schedule, for producing 1.8nm-class chips in the middle of this year. If Intel can prove wrong the rumors about it ...

TechPowerUp, citing Intel’s engineering manager Pankaj Marria, reports that initial 18A wafers are already rolling out from the Arizona plant. The progress, according to ijiwei and Commercial Times, ...

Another interesting trend according to Fischer is the increased market share of rectangular wafers both in the 182mm size (M10R) and 210 mm size (G12R). “This is interesting to see, especially ...

Semiconductor packaging plays a crucial role in modern electronics by protecting the chip, enabling electrical connections, and managing heat dissipation. As the industry moves toward miniaturization, ...

College of Material, Chemistry and Chemical Engineering, Key Laboratory of Organosilicon Chemistry and Material Technology, Ministry of Education, Hangzhou Normal University, Hangzhou 311121, China ...