A gate-level partitioning algorithm based on vertex-degree of undirected graph is proposed for parallel simulation of very large-scale integrate (VLSI) circuit in this paper. Both the inner-and outer ...

George Karypis, Vipin Kumar, Parallel Multilevel k-Way Partitioning Scheme for Irregular Graphs, SIAM Review, Vol. 41, No. 2 (Jun., 1999), pp. 278-300. ... the time taken by our parallel graph ...

This paper describes an algorithm for partitioning a graph that is in the form of a tree. The algorithm has a growth in computation time and storage requirements that is directly proportional to the ...

COMP_ENG 357: Introduction to VLSI CAD VIEW ALL COURSE TIMES AND SESSIONS Prerequisites COMP_SCI 214 Description. CATALOG DESCRIPTION : Basic concepts in VLSI CAD with emphasis on physical design, ...