Extensive investigations and interdisciplinary design considerations, including a DNNbased autoencoder structure, learning framework, and implementation of a low-complexity digital circuit for ...

An 8-bit test chip fabricated with the 65-nm CMOS technology consumed 2.3 mW at 1 GS/s. It also had a sufficiently high signal-to-noise and distortion ratio (SNDR) of 44.4 dB even at the Nyquist ...