This brief presents a 14-bit 4 GS/s time-interleaving ADC design using two interleaved sub-ADCs. The sub-ADC achieves 2 GS/s conversion rate in 28 nm CMOS technology and uses pipelined structure to ...

Bit-slice architectures have been developed to support various bit-precision and data sparsity of deep neural networks (DNNs). However, because of low-bit precision and a wide range of sparsity of bit ...