Block Diagram of the Viterbi Decoder IP Core FPGA IP RT-630-FPGA Hardware Root of Trust Security Processor for Cloud/AI/ML SoC FIPS-140 Complete USB Type-C Power Delivery PHY, RTL, and Software ...

In this paper, the issues of designing a low power VLSI implementation of the Viterbi decoder are addressed. We propose a new improvement in the VLSI architecture of the Add-Compare-Select unit (ACSU) ...

In recent years, the Viterbi algorithm (VA) has been shown to be an efficient trellis decoder for binary and non-binary linear blocks. In our simulation study, the performance of VA decoded non-binary ...