This core supports a vector array of up to 32 fully pipelined DSP units that can perform 32 multiply-accumulates every instruction cycle. It can therefore deliver 8500 MMACs (when performing 32 8 ...

In this paper, we present a domain-specific language, referred to as OptiSDR, that matches high level digital signal processing (DSP) routines for software defined radio (SDR) to their generic ...