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Strategies of parallelizing nested loops on the multicore architectures on the example of the WZ factorization for the dense matrices - IEEE Xplore
In the WZ factorization the outermost parallel loop decreases the number of iterations executed at each step and this changes the amount of parallelism in each step. The aim of the paper is to present ...
IEEE9y
Exploiting parallelism of imperfect nested loops with sibling inner loops on coarse-grained reconfigurable architectures | IEEE Conference Publication | IEEE Xplore
Coarse-grained reconfigurable architecture (CGRA) is a promising platform for loop acceleration, but existing software pipelining methods cannot achieve satisfactory performance on a fair number of ...