The article illustrates techniques for generating parallel logic outputs with industrial serialized digital inputs.

As CMOS device sizes continue to scale down, radiation-related reliability issues are of ever-growing concern. Single event double node upsets (SEDUs) in sequential logic and single event transients ...

In this paper, we present the design, implementation, and evaluation of digital logic circuits using memristor-based technology. The focus is on basic gates, a 2 × 1 multiplexer (MUX), a full adder, a ...