Developed specifically for Xilinx devices, the Active-HDL 4.2XE achieves a 40% increase in simulation speed over the previous, 4.0XE version.With the new tool, users have the ...

Developed for Xilinx devices, the Active-HDL 4.2XE achieves a 40% increase in simulation speed over the previous 4.0XE version. Users now have the ability to seamlessly import ...

Available for All SmartDV Verification IP SAN JOSE, CALIF. –– October 1, 2019 –– SmartDV™ Technologies today announced support for Verilator, the free, open-source hardware description language (HDL) ...

Hardware description language (HDL) simulation is the fundamental means of IC verification. The complexity of modern VLSI is constantly posing serious challenges to HDL simulators. We developed a ...

Wilsonville, Ore.-based Model Technology, a Mentor Graphics company, today releases ModelSim 5.5, a new version of its HDL simulation tool to be used for multimillion gate ASIC and FPGA designs.

Active-HDL 10.1 supports design creation and simulation of the newest industry-leading FPGA devices from Altera®, Lattice®, Microsemi™ (Actel), Quicklogic® and Xilinx®.

Aldec offers a patented technology suite including: design entry, HDL simulators, co-simulation, design rule checking, hardware-assisted verification, co-verification, IP Cores, DO-254 compliance ...