You can use UML sequence diagrams to show the interaction between the proxy, the subject, and the client, using arrows to indicate the messages and lifelines to indicate the objects.

Here's a figure showing the block diagram in Vivado: The interface to this bitfile is defined in example_controller.py. The FPGA code for this project is located in the fpga/redpitaya_example_project ...

Identify the minimal interface that can be retained without breaking the cyclic dependency Expose this 'class interface' as the class structure (guaranteed import cycle-free), much like you would ...