Design and VHDL description of a 32bit multiplier using a Modified Booth Encoding and a Dadda CSA tree. Interactive website for demonstrating or simulating binary multiplication via pencil-and-paper ...

Abstract: The design of a 4*4-bit multiplier using the modified Booth's algorithm in 2- mu m NMOS technology is discussed. The main features of this chip are its 62.5-MHz operating frequency and ...