The folks at Lattice Semiconductor have just announced a LatticeECP2 and LatticeECP2M (“LatticeECP2/M”) FPGA interface reference design supporting the Texas Instruments' ADS6000 family of ...

2. CrossLinkPlus can handle interface conversion in addition to muxing/demuxing of MIPI channels and virtual channels. The FPGA allows the data flowing through chip to be modified.

As FPGA designers strive to achieve higher performance while meeting critical timing margins, one consistently vexing performance bottleneck is the memory interface. Today's more advanced FPGAs ...

As a new Altera® high-performance FPGA, the Cyclone® 4 is used, applications with the Nios® softcore, with its own intelligence are also imaginable. The direct connection of the Cyclone 4 to the ...

Abstract The GRSCRUB is an external Field Programmable Gate Array (FPGA) configuration supervisor developed by Cobham Gaisler as an Intellectual Property (IP) core. The GRSCRUB IP features different ...

FPGA programming using Vivado may take a bit longer for the uninitiated. Commercial C-grade units with an operating temperature range of 0 to 85°C plus a two-year warranty start at $250.

As a new Altera® high-performance FPGA, the Cyclone® 4 is used, applications with the Nios® softcore, with its own intelligence are also imaginable. The direct connection of the Cyclone 4 to the ...

All this is now possible using the Memory Interface Generator (MIG) from Xilinx. This "How To" article will discuss the various memory interface controller design challenges and how to use the MIG to ...