We present the Maestro memory-on-logic 3D-IC architecture for coordinated parallel use of a plurality of systolic arrays (SAs) in performing deep neural network (DNN) inference. Maestro reduces ...

A compact SPICE model was developed to enable circuit-level simulations in EDA tools. We also proposed a method to efficiently control the programmable diode for logic operations in memory arrays, and ...

These gate chains are distributed across multiple logic units in the FPGA and enhance computational efficiency through parallel processing and pipelining techniques.