The block diagram of the Transmitter architecture is given in Figure 2. The input to the transmitter is 64-bit data at 155.50 MHz rate. The output on SPI 4.2 bus is 311 MHz DDR 16-bit data. Hence the ...

In the past, it was super easy to find a block diagram illustrating that architecture on the Web. For Windows 10, I can't find anything. I've found subsystem diagrams, Windows 7 or earlier ...