This project implements a BCD (Binary-Coded Decimal) Adder and Subtractor using Verilog HDL, along with output display logic for 7-segment displays. It includes modules for addition, subtraction, ...

Verilog code has been used to design the proposed BCD adder and it is simulated using ISim. A delay improvement of 9.03% is achieved by the architecture of the BCD adder proposed in this paper.

Multiplier play important role in various applications and in recent years there is an increase in multiplication applications, thereby raising the need for multiplier that performs faster ...