Figure 2. Development model for Stretch's massively parallel architecture, which mates a processor core to reconfigurable FPGA-like fabric, called the Instruction Set Extension Fabric (ISEF). This ...

Learn about common DSP architectures and how they trade-off speed, power, memory, and programmability for digital signal processing applications.

The processor's SIMD portion enables one instruction to be simultaneously executed by a number (two, four, eight, or 16) of DSP processors called parallel datapath units.

Conventional radar signal processing systems have very limited flexibility because they are designed for their specific applications. For this problem, a general purpose high-speed radar signal ...

In this paper, a synchronous dataflow programming method is proposed for programming this architecture, and programming examples are given. Because of its close connection with block diagrams, data ...

[Part 2, BDTI looks at the innovative new tools for massively parallel processors.] In the last few years a number of start-up companies have announced massively parallel processors for embedded DSP ...