The diagram below, which was taken from the Intel paper referenced in the introduction, gives a high-level perspective of the parts that must be added to the cache and memory hierarchy for the ...

1 We will use and treat the terms: “OCP interface†and “OCP port†interchangeable in the article. 2 The final complete set of new signals, new signal encodings, new protocol rules, and new ...

Level 1 and level 2 cache will remain implemented in SRAM, at least for now. And NAND flash memory will remain the king of the NVM hill for low-cost and high-density.

Buffalo Memory’s innovative SATA III SSD is first to implement Spin Torque MRAM as cache memory Embedded Technology 2013 November 18, 2013 08:03 AM Eastern Standard Time ...