Abstract: This paper proposes a novel circuit design of two Ternary Half Subtractor (THS) and a Ternary Full Subtractor (TFS) using Double pass transistor logic (DPL). The proposed THS is implemented ...

Abstract: the descriptive paper proposes the scheme for the conveying half subtractor, that has been implemented by using 2-to-4-line decoder. This paper also expresses switching phenomenon allied ...