ANNAPOLIS, Md. Proclaiming a revolutionary new approach to designing reconfigurable logic, Annapolis Microsystems has announced CoreFire, which allows users to program Annapolis' FPGA-based boards by ...

Intelligent clock gating is key to Xilinx’s bid to reduce dynamic block-RAM (BRAM) power consumption in its Virtex-6 FPGA designs. The key to this fourth generation partial reconfiguration design flow ...

Fifteen years ago verification of FPGA designs was easy but as the size of FPGAs has increased so have the verification challenges, Jerry Kaczynski explains.

Operating temperature requirements require sophisticated heat sink and airflow measurements. The Virtex-5 FPGA System Monitor features on-die temperature and voltage measurement capabilities that ...

Henderson, NV – September 24, 2012 – Aldec, Inc. today announced the immediate availability of Active-HDL™ 9.2, an HDL-based FPGA Design and Simulation solution now offering flexible file ...