Abstract: This paper presents a dual-loop digital delay-locked loop (DLL) for high-speed DRAM applications. The dual-loop architecture using a hybrid (binary + sequential) search algorithm is proposed ...

A C++ library for performing the sequential line search method (which is a human-in-the-loop variant of Bayesian optimization).. The core algorithm is implemented in ...

In this paper, we introduce two design-for-testability (DFT) techniques based on clock partitioning and clock freezing to ease the test generation process for sequential circuits. In the first DFT ...

The core algorithm is implemented in include/sequential-line-search/*.hpp and src/*.cpp.This repository also contains the following example demos: bayesian_optimization_1d: A simple demo of the ...