An array multiplier using the shift and add algorithm was implemented on LT spice. The gates used in the implementation were built using CMOS logic. An assembly language program was also written to do ...

Abstract: This paper presents the simulation results of a 4×4-bit array two phase clocked adiabatic static CMOS logic (2PASCL) multiplier using 0.18 μm standard CMOS technology. We also propose a new ...